AL Tech 8CH Uživatelský manuál Strana 21

  • Stažení
  • Přidat do mých příruček
  • Tisk
  • Strana
    / 36
  • Tabulka s obsahem
  • KNIHY
  • Hodnocené. / 5. Na základě hodnocení zákazníků
Zobrazit stránku 20
21
LTC2424/LTC2428
APPLICATIONS INFORMATION
WUU
U
the 24th rising edge of SCK. On the 24th falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CSADC may remain
LOW and EOC monitored as an end-of-conversion inter-
rupt. Alternatively, CSADC may be driven HIGH setting
SDO to Hi-Z. As described above, CSADC may be pulled
LOW at any time in order to monitor the conversion status.
For each of these operations, CSMUX may be tied to
CSADC without affecting the selected channel.
At the conclusion of the data output cycle, the converter
enters a user transparent calibration cycle prior to actually
performing a conversion on the selected input channel.
This allows a 66ms (for 60Hz notch frequency) settling
time for the multiplexer input. Following the data output
cycle, the multiplexer input channel may be selected any
time in this 66ms window by pulling CSADC HIGH and
serial shifting data into the D
IN
pin, see Figure 14.
While the device is performing the internal calibration, it is
sensitive to ground current disturbances. Error currents
flowing in the ground pin may lead to offset errors. If the
SCK pin is toggling during the calibration, these ground
disturbances will occur. The solution is to either drive the
multiplexer clock input (CLK) separately from the ADC
clock input (SCK), or program the multiplexer in the first
1ms following the data output cycle. The remaining 65ms
may be used to allow the input signal to settle.
Typically, CSADC remains LOW during the data output
state. However, the data output state may be aborted by
pulling CSADC HIGH anytime between the first rising edge
and the 24th falling edge of SCK, see Figure 15. On the
rising edge of CSADC, the device aborts the data output
state and immediately initiates a new conversion. This is
useful for systems not requiring all 24 bits of output data,
aborting an invalid conversion cycle or synchronizing the
start of a conversion.
Internal Serial Clock
This timing mode uses an internal serial clock to shift out
the conversion result and program the multiplexer, see
Figure 16. A CS signal directly drives the CSADC input,
while the inverse of CS drives the CSMUX input. The CS
signal is used to monitor and control the state of the
conversion cycles as well as enable the channel selection.
The multiplexer is programmed during the data output
state. The internal serial clock (SCK) generated by the ADC
is applied to the multiplexer clock input (CLK).
Figure 14. Use of Look Ahead to Program Multiplexer After Data Output
SCK/CLK
SDO
CONVERTER
STATE
D
IN
CSADC/
CSMUX
MSB
EXRSIG
BIT0
LSB
BIT4BIT19BIT18BIT20BIT21BIT22BIT23
24248 F14
TEST EOC
CONV SLEEP DATA OUTPUT INTERNAL CALIBRATION
66ms CALIBRATION
CONVERSION ON SELECTED CHANNEL
DON’T CARE DON’T CAREEN D2 D1 D0
Hi-Z
TEST EOC
66ms CONVERT
133ms CONVERSION CYCLE (OUTPUT RATE = 7.5Hz)
Zobrazit stránku 20
1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 35 36

Komentáře k této Příručce

Žádné komentáře